Séminaire du Collège de France (donné à l’INRIA Sophia-Antipolis)
Intervenants : Laurent Maillet-Contoz et Matthieu Moy La complexité grandissante des circuits intégrés modernes a donné lieu à de nouveaux types de circuits, qu’on appelle systèmes sur puces. Il n’est aujourd’hui plus possible d’attendre les premiers prototypes physiques pour valider la bonne intégration de leurs composants et développer le logiciel embarqué, souvent de taille considérable. Il est donc nécessaire d’utiliser des prototypes virtuels des circuits tôt dans le flot de conception du système global. Dans cet exposé bicéphale, nous présentons les techniques de prototypage virtuel basées sur (...)
Slides presented at DATE 2013
The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycle-accurate simulation, and would be inefficient on loosely timed systems since they cannot run in (...)
Presented at the 20 years of Verimag workshop
This talk summarizes the work on Transaction-Level Models performed in the Synchrone team of the Verimag laboratory between 2002 and 2012.
Real-Time Calculus (RTC) is a framework to analyze heterogeneous real-time systems that process event streams of data. The streams are characterized by arrival curves which express upper and lower bounds on the number of events that may arrive over any specified time interval. System properties may then be computed using algebraic techniques in a compositional way. The property of causality on arrival curves essentially characterizes the absence of deadlock in the corresponding generator. A mathematical operation called causality closure transforms arbitrary curves into (...)
Presented at MEMOCODE 2011
Today’s consumer electronics industry uses modeling and simulation to cope with the complexity and time-to-market challenges of designing high-tech devices. In such context, Transaction-Level Modeling (TLM) is a widely spread modeling approach often used in conjunction with the IEEE standard SystemC discrete-event simulator. In this paper, we present a novel approach to modeling time that distinguishes between instantaneous actions and tasks with a duration. We argue that this distinction should be natural to the user. In addition, we show that it gives us important insight and better (...)
Presented at "Journées Compilation à Dinard", April 2011
SystemC is the industry-standard tool for high-level modeling of System-on-Chips. It provides a simulation kernel to model the parallelism of the chip, a notion of components and communication primitives. SystemC is implemented as a C++ library, which means a SystemC program can be compiled with a plain C++ compiler. However, we show in this talk that plain C++ compilers lack information about the program. SystemC-specific compilation techniques, combining knowledge of the static part of the program with the dynamically-created (...)
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorporates timing and concurrency concepts. A SystemC program is typically processed by a SystemC front-end in order to verify, debug and/or optimize the architecture. Designing a SystemC front-end is a difficult task and existing approaches suffer from (...)
Informal talk given at the HELP meeting
We present quick experiments made with the TLM-Power library on a simple TLM platform. The TLM-Power library is modified to become more generic first, and the platform is modified to handle a "sleep" instruction, and a DVFS.
SystemC is a widely used tool for prototyping Systems-on-a-Chip. Being implemented as a C++ library, a plain C++ compiler is sufficient to compile and simulate a SystemC program. However, a SystemC program needs to be processed by a dedicated tool in order to visualize, formally verify, debug and/or optimize the architecture. In this paper we focus on the tools (called front-ends) used in the initial stages of processing SystemC programs. We describe the challenges in developing SystemC front-ends and present a survey of existing solutions. The limitations and (...)
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