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Bruno Ferres
Post-doc at LIP, https://www.linkedin.com/in/bruno-ferres/?originalSubdomain=fr
Articles
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Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
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Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
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Improving Diagnosis Quality and Performances of a Formal Verification Tool for Electric Circuits at Transistor Level
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[TAKEN] Dedicated Solver for Formal Verification of Electric Circuits with Multiple Power Supplies
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