Master Internship Proposal
Friday 10 December 2010
SystemC is a C++ library that allows modeling complex hardware systems at a high level of abstraction (typically, Systems-on-a-Chip contained in smartphones, set-top-boxes, ...).
The parallelism of the model is expressed with SystemC processes, which are executed sequentially during simulation (we call this "cooperative" simulation). Cooperative simulation brings a relative comfort to the user, since most accesses to shared variables do not need to be protected with locks (mutex). However, this is also an important limitation of SystemC, since it forces the simulation to be executed on a single processor, and do not always allow the modeling of all the behaviors of the hardware.
We are investigating compromises between cooperative and parallel (or "preemptive") simulation.
The students must have good skills in concurrent programming, and be familiar with the C++ language.
The SYNCHRONE team of the Verimag laboratory has been working on SystemC for almost 10 years, on various issues (formal and runtime verification, methodology, parallelisation, ...). In addition, we've implemented an alternate simulator called jTLM on which we already experimented various approaches to parallelism. After these experimentations, we are looking for ways to introduce these concepts in the semantics of SystemC.
The internship should consist in several steps:
In parallel with this, of course, a bibliogriphical work will be needed on previous approaches (within the laboratory and in other teams).
As any research work, the subject is to be refined by discussing with the supervisors. Don't hesitate to contact us for discussion!