Parallel SystemC/TLM Simulation of Hardware Components described for High-Level Synthesis
Thursday 1 December 2016
Systems on chip consist in a hardware part (an integrated circuit) and a software part (a program) that uses the hardware resources of the chip. Consequently, the embedded software is intrinsically connected to the chip hardware. Hardware acceleration components are key differentiation factors from one product to another. It is necessary to simulate systems on chip very early in the design flow; before the chip is physically available and even before its full specification. For such simulations, developers write a model of the system on chip in SystemC, at the TLM (Transaction Level Modeling) abstraction level. The hardware part of a chip consists in components that behave in parallel with each other. However, the reference SystemC simulator execute simulations sequentially. The sequential execution enables to keep good properties of SystemC simulations, namely reproducibility and ease of model writing. This thesis work address the parallel execution of SystemC/TLM simulations. The goal of parallel simulation is to speed up simulations in the context of the model development, where it is important to quickly get results. In order to identify the performance problem of complex models at STMicroelectronics, the first step of this thesis was to analyse the execution profile of a case study, representative of the complexity of current platforms. For this study, we developed a trace recording and visualization tool. The results of this study indicated that the performance critical parts of the simulation are hardware acceleration components. Studying existing parallel simulation approaches led us to look for other parallel simulation techniques. To speed up the development of hardware acceleration components and increase the reusability from one project to another, the HLS (High Level Synthesis) design flow is used notably at STMicroelectronics. This design flow enables to generate a logically synthesizable model of a component from a high level behavioral description in C++. This design flow also constraints the development: it is split in sub-functions assembled in a pipeline. The code written for HLS must be re-used in SystemC/TLM models: this situation will become more and more frequent and there is no time to rewrite the models of such components within short delays. We developed a parallel simulation infrastructure enabling the integration and efficient simulation of hardware components written for HLS. We applied this infrastructure to an example platform which resulted in speeding up the simulation. Beyond this result, one of the main conclusion of this thesis is that parallel simulation of abstract SystemC/TLM models will require to combine multiple parallelization techniques. Future research work can identify other types of potential parallelism in industrial models. This will become critical with the new challenges of simulation as multi-physical simulations and internet of things.
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