Code Generation for Multi-Core Processor with Hard Real-Time Constraints
Thursday 1 December 2016
Most critical systems are subject to hard real-time requirements. These systems are more and more complex and the computational power of the predictable single-core processors is no longer sufficient.Multi- or many-core architectures are good alternatives but interferences on shared resources must betaken into account to avoid unpredictable timing effects. For many-core, the Network-on-Chip (NoC)must be configured such that deadlocks are avoided and a tight Worst-Case Traversal Time (WCTT)of the communications can be computed. The Kalray MPPA2 is a many-core architecture with good timing properties. Dataflow Synchronous languages such as Lustre or Scade are widely used for avionics critical software. In these languages, programs are described by networks of computational nodes. We introduce a method to extract parallel tasks from synchronous programs. Then, we generate parallel code to deploy tasks on the chip and implement NoC and shared-memory communications. The generated code enables traceability. It is based on a time-triggered execution model which relieson a static schedule and minimizes the memory interferences thanks to usage of memory banks.The code enables the computation of a worst-case execution time bound accounting for the memory interferences and the WCTT of NoC transmissions. We generate a configuration of the platform to enable a fair bandwidth attribution on the NoC, bounded transmissions through the NoC and clock synchronization. Finally, we apply this tool chain on avionic case studies and synthetic benchmarks running on 64 cores.