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Amaury Graillat (PhD)

Code Generation for Multi-Core Processor with Hard Real-Time Constraints

Thursday 1 December 2016

Years: 2015, 2016, 2017, 2018 (CIFRE Ph. D)
Co-supervisor: Pascal Raymond
Subject: Code Generation for Multi-Core Processor with Hard Real-Time Constraints
Abstract:

Most critical systems are subject to hard real-time requirements. These systems are more and more complex and the computational power of the predictable single-core processors is no longer sufficient.Multi- or many-core architectures are good alternatives but interferences on shared resources must betaken into account to avoid unpredictable timing effects. For many-core, the Network-on-Chip (NoC)must be configured such that deadlocks are avoided and a tight Worst-Case Traversal Time (WCTT)of the communications can be computed. The Kalray MPPA2 is a many-core architecture with good timing properties. Dataflow Synchronous languages such as Lustre or Scade are widely used for avionics critical software. In these languages, programs are described by networks of computational nodes. We introduce a method to extract parallel tasks from synchronous programs. Then, we generate parallel code to deploy tasks on the chip and implement NoC and shared-memory communications. The generated code enables traceability. It is based on a time-triggered execution model which relieson a static schedule and minimizes the memory interferences thanks to usage of memory banks.The code enables the computation of a worst-case execution time bound accounting for the memory interferences and the WCTT of NoC transmissions. We generate a configuration of the platform to enable a fair bandwidth attribution on the NoC, bounded transmissions through the NoC and clock synchronization. Finally, we apply this tool chain on avionic case studies and synthetic benchmarks running on 64 cores.


2018

Conference papers

ref_biblio
Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. Parallel Code Generation of Synchronous Programs for a Many-core Architecture. DATE 2018 - Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. IEEE, pp.1139-1142, 2018, 〈https://www.date-conference.com/〉. 〈10.23919/DATE.2018.8342182〉. 〈hal-01667594v2〉
Accès au texte intégral et bibtex
https://hal.inria.fr/hal-01667594/file/date2018.pdf BibTex
ref_biblio
Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, Lionel Havet. Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor. ERTS 2018 - 9th European Congress on Embedded Real Time Software and Systems, Jan 2018, Toulouse, France. 〈hal-01707911〉
Accès au texte intégral et bibtex
https://hal.archives-ouvertes.fr/hal-01707911/file/Version-Finale.pdf BibTex

Reports

ref_biblio
Keryan Didier, Dumitru Potop-Butucaru, Guillaume Iooss, Albert Cohen, Jean Souyris, et al.. Parallelisation efficace de larges applications temps-reel. [Research Report] RR-9180, INRIA Paris. 2018. 〈hal-01810176v2〉
Accès au texte intégral et bibtex
https://hal.inria.fr/hal-01810176/file/RR-9180.pdf BibTex

Theses

ref_biblio
Amaury Graillat. Génération de code pour un many-core avec des contraintes temps réel fortes. Langage de programmation [cs.PL]. Université Grenoble Alpes, 2018. Français. 〈NNT : 2018GREAM063〉. 〈tel-02069346〉
Accès au texte intégral et bibtex
https://tel.archives-ouvertes.fr/tel-02069346/file/GRAILLAT_2018_archivage.pdf BibTex

2017

Reports

ref_biblio
Keryan Didier, Albert Cohen, Adrien Gauffriau, Amaury Graillat, Dumitru Potop-Butucaru. Sheep in wolf's clothing: Implementation models for data-flow multi-threaded software. [Research Report] RR-9057, Inria Paris. 2017, pp.31. 〈hal-01509314〉
Accès au texte intégral et bibtex
https://hal.inria.fr/hal-01509314/file/RR-9057.pdf BibTex

Attached documents


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