Code Generation for Simulation using SystemC
Monday 8 October 2018
The internship took place in Lyon, France, at LIP (Laboratoire de l’Informatique du Parallélisme), which is associated with CNRS (Centre national de la recherche scientifique), ENS (École Normale Supérieure) de Lyon, INRIA (Institut National de Recherche en Informatique et en Automatique) and Université Claude Bernard Lyon 1. The team in which I worked is the CASH team. Its name stands for Compilation and Analyses, Software and Hardware, which slightly sums up their interest and vision. The need of optimized software or hardware compilation for high-performance computing (HPC) with data-intensive computations has been noticed during the last years. It is the goal of the CASH team to find ways in which complex HPC applications can be handled. The transverse and fundamental topic of CASH can be expressed in one word: dataflow. The CASH team wants to create a flow, expressed in Figure 1, in which C code can be processed into parallel code using a suitable dataflow model. After that, the code has to be synthesized using high-level synthesis tools. In the particular case of this research, the chosen tool is Vivado HLS. The synthesized code will be finally mapped on the FPGA. Simulation is a very important part of complex hardware programming, since it provides an environment in which debugging takes less time, no setup time is needed and it helps to discover whether the problem appears in hardware or in software. In order to fulfill the task efficiently in terms of time and resources, simulation of the generated code is highly needed. Another reason why simulation is required is the fact that the dataflow model is hard to debug and the code used for simulation would help to easily detect bugs. The task that I worked on was writing a tool which provides code generation for simulation in SystemC.