List publication All in one, By year.
Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi, Jérôme Cornet,
Laurent Maillet-Contoz, and Ilija Materic.
Co-Simulation of Functional SystemC TLM Models with Power/Thermal
In Virtual Prototyping of Parallel and Embedded Systems
(VIPES), Boston, US, May 2013.
[ bib |
Modern systems-on-chips need sophisticated power-management policies to control their power consumption and temperature. These power-management policies are usually implemented partly in software, with hardware support. They need to be validated early, hence power and temperature-aware simulation techniques at the system-level need to be developed. Existing approaches for system-level power and thermal analysis usually either completely abstract the functionality (allowing only simple scenarios to be simulated), or run the functional simulation independently from the non-functional one. The approach presented in this paper allows a coupled simulation of a SystemC/TLM model, possibly including the actual embedded software, with a power and temperature solver such as ATMI or the commercial tool ACEplorer. Power and temperature analysis is done based on the stimuli sent by the SystemC/TLM platform, which in turn can take decisions based on the non-functional simulation.
Parallel Programming with SystemC for Loosely Timed Models: A
In The Design, Automation, and Test in Europe (DATE),
Grenoble, France, March 2013.
16.4% accepted as long-paper, Rank A+ GDR SoC-SiP.
[ bib |
The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycle-accurate simulation, and would be inefficient on loosely timed systems since they cannot run in parallel processes that do not execute simultaneously. We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. Our tool exploits this notion of duration to run the simulation in parallel. It runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. This allows the user to focus on the performance-critical parts of the program that need to be parallelized.
Keywords: SystemC; TLM; parallelism; multi-core; loosely-timed
|||Tayeb Bouhadiba, Matthieu Moy, and Florence Maraninchi. System-level modeling of energy in TLM for early validation of power and thermal management. In Design Automation and Test Europe (DATE), Grenoble, France, March 2013. 16.4% accepted as long-paper, Rank A+ GDR SoC-SiP. [ bib | http | .pdf ]|
|||Claude Helmstetter and Matthieu Moy. LIBTLMPWT: Model power-consumption and temperature in systemc/tlm. Published as Free Software (GPL License), 2013. [ bib | http ]|
Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, and
Fast and Accurate TLM Simulations using Temporal Decoupling for
In Design, Automation and Test in Europe (DATE), page 1185,
Grenoble, France, Mar 2013.
acceptance rate: 302/829 = 36.4% all categories, Rank A+ GDR
[ bib |
Untimed models of large embedded systems, generally written using SystemC/TLM, allow the software team to start simulations before the RTL description is available, and then provide a golden reference model to the verification team. For those two purposes, only a correct functional behavior is required, but users are asking more and more for timing estimations early in the design flow. Because companies cannot afford to maintain two simulators for the same chip, only local modifications of the untimed model are considered. A known approach is to add timing annotations into the code and to reduce the number of costly context switches using temporal decoupling, meaning that a process can go ahead of the simulation time before synchronizing again. Our current goal is to apply temporal decoupling to the TLM platform of a many-core SoC dedicated to high performance computing. Part of this SoC communicates using classic memory-mapped buses, but it can be extended with hardware accelerators communicating using FIFOs. Whereas temporal decoupling for memory-based transactions has been widely studied, FIFO-based communications raise issues that have not been addressed before. In this paper, we provide an efficient solution to combine temporal decoupling and FIFO-based communications.
This file was generated by bibtex2html 1.98.