2006.bib

@comment{{This file has been generated by bib2bib 1.98}}

@comment{{Command line: /usr/bin/bib2bib matthieu_moy.bib -c year=2006 -ob 2006.bib}}

@article{lussy-journal,
  author = {Matthieu Moy and Florence Maraninchi and Laurent Maillet-Contoz},
  title = {{LusSy}: an open Tool for the Analysis of Systems-on-a-Chip at the Transaction Level},
  journal = {Design Automation for Embedded Systems},
  year = 2006,
  note = {special issue on {SystemC}-based systems},
  url = {http://www-verimag.imag.fr/~moy/publications/springer.pdf},
  abstract = {We describe a toolbox for the analysis of
                  Systems-on-a-chip written in {SystemC} at the
                  transaction level. The tool is able to extract
                  information from {SystemC} code, and to build a set of
                  parallel automata that capture the semantics of a
                  {SystemC} design, including the transaction-level
                  specific constructs. As far as we know, this
                  provides the first executable formal semantics of
                  {SystemC}. Being implemented as a traditional compiler
                  front-end, it is able to deal with general {SystemC}
                  designs. The intermediate representation is now
                  connected to existing formal verification tools via
                  appropriate encodings. The toolbox is open and other
                  tools will be used in the future.}
}

@online{framogr-software,
  author = {Matthieu Moy and V. H. Gupta and K. Gopinath},
  title = {{Framogr}: a {FRAMework} for the {MOdeling} and simulation of {GRoup} protocols},
  howpublished = {Published as Free Software (LGPL License)},
  year = 2006,
  note = {\url{http://download.gna.org/framogr/}}
}

@article{helmstet:fmcad06,
  author = {Claude Helmstetter and Florence Maraninchi and Laurent Maillet-Contoz and Matthieu Moy},
  title = {Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip},
  journal = {{FMCAD}},
  year = {2006},
  isbn = {0-7695-2707-8},
  pages = {171-178},
  doi = {http://doi.ieeecomputersociety.org/10.1109/FMCAD.2006.10},
  publisher = {IEEE Computer Society},
  address = {Los Alamitos, CA, USA},
  url = {http://www-verimag.imag.fr/~moy/publications/Helmstetter_FMCAD06.pdf},
  abstract = {{SystemC} is becoming a de-facto standard for the
early simulation of Systems-on-a-chip (SoCs). It is a parallel
language with a scheduler. Testing a SoC written in {SystemC}
implies that we execute it, for some well chosen data. We are
bound to use a particular deterministic implementation of the
scheduler, whose specification is non-deterministic. Consequently,
we may fail to discover bugs that would have appeared using
another valid implementation of the scheduler. Current methods
for testings SoCs concentrate on the generation of the inputs,
and do not address this problem at all. We assume that the
selection of relevant data is already done, and we generate
several schedulings allowed by the scheduler specification. We
use dynamic partial-order reduction techniques to avoid the
generation of two schedulings that have the same effect on
the system’s behavior. Exploring alternative schedulings during
testing is a way of guaranteeing that the SoC description, and
in particular the embedded software, is scheduler-independent,
hence more robust. The technique extends to the exploration of
other non-fully specified aspects of SoC descriptions, like timing.},
  note = {Acceptance rate: 21/90 = 23\%}
}

This file was generated by bibtex2html 1.98.