Années:
2015
(
M2R)
Co-encadrant:
Florence Maraninchi
Sujet: Towards Semantics-Preserving Implementation of Synchronous Programs on Many-Core Architectures
Résumé: Reactive systems are systems that constantly react to their environment. One must guarantee that the computation time of the system is bounded and matches the input-output latency
imposed by the environment (for instance the period of measure of the altitude for a flight control system). We talk about multi-periodic systems when the nodes of a program are running
at different periods. Today, reactive programs are more and more complex, and we reach the
limit of the single-processors in term of computation. Consequently, the size of the program
is limited to match the time requirements. Most of the processors are multi or many-core. But
they are complex and the Worst-Case Execution Time of a program executed on these architectures does not guarantee the time requirement. Yet, the Kalray MPPA many-core architecture
is predictable and allows to bound both the execution and the transmission time between the
many-core clusters.
Our purpose is to run synchronous programs on many-core architectures with bounded
delays. On one hand, we consider a synchronous program composed of several nodes communicating together, on the other hand a many-core chip composed of several clusters and a
Network-On-Chip (NoC). The first problem is to find a way to map the nodes on the clusters.
The other problem is to give the semantics of the communication between the nodes. The
semantics must be deterministic and preservable when implemented on the many-core architecture to guarantee equivalence between the synchronous program and the implementation.
We give a deterministic semantics to communications between the nodes of different periods.
We give the implementation of a multi-periodic program on the Kalray MPPA. Finally, we
evaluate our solution by testing. Our method provides a key element toward the deterministic
implementation of reactive programs on many-core architecture : a way to preserve a centralized deterministic semantics of a multi-periodic program, when the program parts exchange
information via the NoC.
2020
Journal articles
- ref_biblio
- Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge. Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. Performance Evaluation, 2020, 143, pp.102124. ⟨10.1016/j.peva.2020.102124⟩. ⟨hal-03170466⟩
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2019
Journal articles
- ref_biblio
- Keryan Didier, Dumitru Potop-Butucaru, Guillaume Iooss, Albert Cohen, Jean Souyris, et al.. Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware. ACM Transactions on Architecture and Code Optimization, 2019, 16 (3), pp.1-27. ⟨10.1145/3328799⟩. ⟨hal-02422789⟩
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Conference papers
- ref_biblio
- Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip. RTNS 2019 - 27th International Conference on Real-Time Networks and Systems, Nov 2019, Toulouse, France. pp.61-69, ⟨10.1145/3356401.3356416⟩. ⟨hal-02320463⟩
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Preprints, Working Papers, ...
- ref_biblio
- Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge. Comparing strategies to bound the latencies of the MPPA Network-on-Chipi (Extended version). 2019. ⟨hal-02122874⟩
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- ref_biblio
- Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge. Comparing strategies to bound the latencies of the MPPA NoC. 2019. ⟨hal-02099698⟩
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2018
Conference papers
- ref_biblio
- Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. Parallel Code Generation of Synchronous Programs for a Many-core Architecture. DATE 2018 - Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. pp.1139-1142, ⟨10.23919/DATE.2018.8342182⟩. ⟨hal-01667594v2⟩
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- ref_biblio
- Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, Lionel Havet. Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor. ERTS 2018 - 9th European Congress on Embedded Real Time Software and Systems, Jan 2018, Toulouse, France. ⟨hal-01707911⟩
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Reports
- ref_biblio
- Keryan Didier, Dumitru Potop-Butucaru, Guillaume Iooss, Albert Cohen, Jean Souyris, et al.. Efficient parallelization of large-scale hard real-time applications. [Research Report] RR-9180, INRIA Paris. 2018. ⟨hal-01810176v2⟩
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Theses
- ref_biblio
- Amaury Graillat. Génération de code pour un many-core avec des contraintes temps réel fortes. Langage de programmation [cs.PL]. Université Grenoble Alpes, 2018. Français. ⟨NNT : 2018GREAM063⟩. ⟨tel-02069346⟩
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2017
Reports
- ref_biblio
- Keryan Didier, Albert Cohen, Adrien Gauffriau, Amaury Graillat, Dumitru Potop-Butucaru. Sheep in wolf's clothing: Implementation models for data-flow multi-threaded software. [Research Report] RR-9057, Inria Paris. 2017, pp.31. ⟨hal-01509314⟩
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