Home > Research > Talks > Transaction-Level Models of Systems-on-a-Chip: Can they be Correct, (...)
Transaction-Level Models of Systems-on-a-Chip: Can they be Correct, Faithful and Fast?
Presented at the 20 years of Verimag workshop
Friday 17 May 2013
This talk summarizes the work on Transaction-Level Models performed in the Synchrone team of the Verimag laboratory between 2002 and 2012.
Attached documents
-
Slides
17 May 2013
info document : PDF
1.7 Mb
Email:
Keywords
Also in this section
- Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip
- Pourquoi et comment se lancer dans le libre quand on est étudiant (ou pas) ?
- Transaction-Level Models of Systems-on-a-Chip Can they be Fast, Correct and Faithful?
- Prototypage virtuel de système sur puce pour une simulation rapide et fidèle
- Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach
- Transaction-Level Models of Systems-on-a-Chip: Can they be Correct, Faithful and Fast?
- Causality Closure for a New Class of Curves in Real-Time Calculus
- Modeling of Time in Discrete-Event Simulation of Systems-on-Chip
- PinaVM and Tweto: Compilation and Optimization Techniques for SystemC
- PinaVM: a SystemC Front-End Based on an Executable Intermediate Representation
| Log in |
Site Map |
Graphic design (c) styleshout under License Creative Commons Attribution 2.5 License