Wednesday 25 September 2013
SystemC is a C++ library that allows modeling complex hardware systems. It has become an unavoidable tool in the design-flow of Systems-on-a-Chip (included in mobile-phones, set-top-boxes, ...).
Parallelism of the embedded system is modeled with SystemC processes, which are executed sequentially during simulation (we refer to this as "cooperative" simulation). Cooperative simulation brings some comfort to the user, since most access to shared variables do not need particular protection and locking (mutex), but it is also an important limitation of SystemC, since it forces the simulation to execute on a single processor. On today's machines, not being able to exploit the host machine's parallelism is an important bottleneck, and the absence of parallelism in SystemC will clearly become a major concern on tomorrow's machines.
We are looking for compromises between cooperative simulation and parallel simulation. The tool sc-during already allows running some tasks in parallel with a SystemC cooperative simulation.
The goal of this project is to provide use-cases for the sc-during tool, and to evaluate its performances on some non-trivial examples.
The candidate should be experienced with parallel programming.
Knowledge of C++ is a plus (since SystemC is based on C++), but it is clearly possible to learn the C++ notions required quickly with a strong knowledge of C and object oriented programming.
Knowledge of French is not a pre-requisite.
The SYNCHRONE team of the Verimag laboratory have been working on modeling of Systems-on-a-Chip and SystemC for ten years, on various aspects. This research have been carried out in close collaboration with STMicroelectronics (4 CIFRE Ph.D, including the one of Matthieu Moy, in common with the SYNCHRONE team).
A Ph.D student will be working on improving the sc-during tool, and will interact with this project.