Accueil > Recherche > Étudiants/Post-docs > Ligia Novacean

Ligia Novacean


lundi 8 octobre 2018

Années: 2018 (Stage L3)
Co-encadrant: Christophe Alias

This internship took place at LIP (Laboratoire de l’Informatique du Parallelisme), a computer science laboratory in Lyon, associated with CNRS, ENS Lyon, INRIA and UCB Lyon 1. As an intern, I was part of a research team, namely CASH (Compilation and Analysis, Software and Hardware). The main objective of CASH is to provide energy-efficient software and hardware compilation techniques by taking advantage of architectures like multi-core processors, GPUs or FPGAs. Today’s FPGAs are an efficient solution for performing advanced computing. FPGA accelerators allow for tremendous parallelism : one board provides parallel computing resources numbering in millions. Usually, FPGAs are configured by means of Hardware Descriptive Languages (e.g. Verilog, VHDL). However, for reducing the development effort and the need of FPGA electronics knowledge, High-Level Synthesis languages like Vivado HLS have been introduced. Vivado HLS takes as input a C specification and generates the corresponding HDL description. Vivado HLS can structure functions in the input code as a single state machine or extract a limited level of parallelism from it. One of CASH team’s projects has as objective mapping C code to massively parallel FPGA accelerators. For enhancing the level of extracted parallelism, the team developed Dcc-light. Dcc-light is a parallelism extraction compiler that outputs a dataflow representation named DPN (data-aware process network). Therefore, the input C code will not be mapped directly to an FPGA board using Vivado HLS. Instead, parallelism is extracted from the input program using Dcc-light as a DPN program. Afterwards, we convert the DPN intermediate representation into a subset of C code. The obtained C program is provided as input to Vivado HLS, which synthesizes the circuit to be mapped on the FPGA, as seen in Figure 1. Besides these transformations, the DPN is also used within SystemC code generation for simulation purposes. The main tasks I was in charge of were to generate and optimize the C code for high-level synthesis. My work included experimenting with several tools and topics such as Vivado HLS and its optimization strategies, the DPN intermediate dataflow representation and, finally, a code generation algorithm.

Documents joints

  • 8 octobre 2018
    info document : PDF
    457.1 ko

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